Interval representation of logic signals suggested to estimation of the test sequences length for faults in digital circuits with memory. Developed pseudo-Boolean algebra over a set of intervals, which defines the operations that are analogous to logical disjunction, conjunction, and inversion,...

A genetic tests synthesis algorithm for the synchronous digital circuits, based on solving the integer optimization problem with a scalar objective function is presented. A decomposition strategy of the circuit under test and symbolic representation of its fragments obtained. New objective...